In the EEPROM memories, the logical value of a bit stored in a memory element is represented by the value of the threshold voltage of a floating-gate transistor, which can be modified at will by programming or erasing operations. The programming or the erasing of a floating-gate transistor consists of the injection or the extraction of the electrical charges into or from the gate of the transistor by tunnel effect (Fowler-Nordheim effect) by means of a high voltage Vpp which can be of the order of 10 to 20 volts, typically 13 volts.
This high voltage of 13 volts, needed for the writing of EEPROM memories, is non-reducible and is very constraining as regards the fabrication technology and the reliability of the product.
Indeed, lithographic reduction, in other words the increase in the etch resolution, leads to a decrease in the operating voltages, and this high writing voltage becomes more problematic in terms notably of leakages of the source/drain junctions of the transistors and also in terms of breakdown of the gate oxides.
As a consequence, these risks of breakdown and of premature aging of the transistors have a direct impact on the reliability of the product.
One solution, referred to as “split voltage” according to a terminology normally used by those skilled in the art, has been envisaged. More precisely, the high voltage Vpp required for the programming of the memory planes is split between a positive voltage Vpp+ and a negative voltage Vpp− such that the difference (Vpp+−Vpp−) is equal to Vpp. Thus, in such an approach, a voltage Vpp+ of the order of 4 volts and a voltage Vpp− of the order of −9 volts will be chosen.
Such a solution allows the constraint on the voltage capability of the transistors to be relaxed. However, it has the drawback of rendering the fabrication process for the memory planes more complicated since it generally requires a technology known as “triple well” owing to the negative voltage of the order of a few volts. Furthermore, the design of the control is more complicated since it is necessary to provide negative voltage switching operations, which also has a negative impact on the surface area of the memory plane. Indeed, a negative voltage switching element proves to be costly in space occupied in the memory plane (use of PMOS transistors) as regards the transistors for selection of the control gates.
Furthermore, in a conventional non-volatile memory device, comprising a matrix memory plane comprising columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row, these control elements are generally distributed over every other column of the memory plane.
This results notably in a periodic rupture of the uniformity of the memory plane.
Furthermore, this periodic rupture in the uniformity of the memory plane generally causes variations in the behavior of the memory cells near to the control elements.
These variations in behavior are conventionally reduced by the addition of inactive structures along the edges of the memory blocks, which has a negative impact in terms of surface area occupied.